Qblox Cluster
How Q1 sequence processors are linked.
Within a module. Between modules. Between clusters.
Free pulse scheduling
Pulses land anywhere on a fine time grid, so short pulses are never rounded to coarse clock edges.
1 ns
Pulse placement time grid
4 ns
Real-time parameter update
Ultra-fast spectroscopy
Hardware-driven frequency chirping sweeps qubit frequency on-sequencer for fast characterisation.
Multi-channel readout and control
Up to 8 frequencies multiplexed within an 800 MHz band from one channel, with phase tracked in hardware.
Photon time-tagging
Timetag sequencers record photon arrival times for trapped-ion, cold-atom, and quantum-network setups.
On-board qubit calibration
On-sequencer routines, including golden-section search, recalibrate resonance frequency, qubit frequency, gate amplitude, and T1 without interrupting an experiment.
Real-time predistortion
Cable, bias-tee, and chip distortion cancelled on-FPGA before the pulse reaches the qubit.
QECi
Vendor-agnostic decoder interface
Connect the Cluster to any QECi-compliant decoder for real-time error correction across codes and decoders, demonstrated in a full QEC loop with Riverlane’s Deltaflow 2.
Round-trip latency
6.886 µs
on Surface-17
11.886 µs
on Surface-161
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NVIDIA NVQLink
GPU-accelerated hybrid quantum-classical control
Connect the Cluster to NVIDIA GPUs through NVQLink for real-time decoding and calibration, then scale the same code to data center GPUs.
Round-trip latency
<4.0 µs
on RTX PRO 6000 Blackwell
<7.2 µs
on DGX Spark
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Real-Time Precision at Scale Across Every Level
Every added channel brings its own Q1, with the same time grid and update rate, so timing behavior at 5 qubits holds at 100+.
Control sequencers
Govern signal generation
Readout sequencers
Govern signal generation and signal acquisition together, enabling on-sequencer measurement and state discrimination.
Timetag sequencers
Govern the output and acquisition of TTL signals, used for time-correlated event timing.
At a glance
PULSE PLACEMENT RESOLUTION:
1 ns time grid
REAL-TIME PARAMETER UPDATE RATE:
4 ns
PULSE PLAYBACK:
gapless, back to back, with parameters updated between pulses
FREQUENCY MULTIPLEXING:
up to 8 tones within 800 MHz, per sequencer
REAL-TIME PREDISTORTION:
inverse high-pass filter plus 4x IIR and FIR stages, on-FPGA
HOST DEPENDENCY:
none, fully on-FPGA execution
SEQUENCER TYPES:
control, readout, timetag
PROGRAMMING INTERFACE:
Qblox Scheduler (high level)
Qblox Instruments API (low level)
Q1ASM open instruction set
Qblox Instruments API (low level)
Q1ASM open instruction set
SEQUENCERS PER MAINFRAME:
Up to 120 Q1 sequencers per mainframe
Who this is for
Quantum hardware companies.
Every added qubit should add hardware, not a control redesign. Q1 keeps the per-channel footprint small, Clusters extend the same clock and feedback network linearly, and open interfaces let your own compiler and decoder drive the stack with no lock-in.
National labs / government research.
Multi-year programs need results that reproduce run after run, and control that connects to existing HPC. Every real-time decision runs in a fixed hardware window, the QEC loop is benchmarked with Riverlane's Deltaflow 2, and NVQLink connects Q1 sequencers to GPU-accelerated decoding under CUDA-Q.
Frequently asked questions
What is Q1?
Q1 is the real-time sequence processor implemented in the FPGA of every Qblox module. Each Q1 sequencer runs independently, like a core in a CPU, generating, timing, and shaping pulses locally in hardware with no host computer in the loop.
How fast is Q1?
Q1 places pulses on a 1 ns time grid and updates pulse parameters in 4 ns, deterministically, on every cycle.
What is gapless playback, and why does it matter?
Gapless playback means Q1 plays pulses with different parameters back to back, with no idle time in between. Q1 separates its classical core from its real-time core, so logic and calculations never interrupt the pulse stream. Circuits run more compactly, and qubits do not decohere while the controller computes.
Why does a 1 ns time grid matter?
A 1 ns grid is four times finer than the FPGA clock. Pulses start exactly where the schedule places them, rather than rounding to a coarser clock edge, which gives short pulses full scheduling freedom.
Is Q1's timing deterministic or statistical?
Deterministic. Every operation completes within a fixed hardware window, independent of system load. Software-timed control that relies on host computation completes within a statistical range instead.
Why not precalculate the full pulse sequence and load it into memory?
Precalculated sequences are slow to upload and cannot adapt to qubit measurements while running. Q1 generates parameterized pulses on the fly, so control flow can change mid-sequence and uploads stay small.
How does Q1 time-tag photons?
Q1-based timetag modules detect photon arrival times with dedicated time-tagging hardware rather than ADC sampling. They support cold-atom, trapped-ion, and quantum-network setups.
What is real-time predistortion (RTP)?
RTP is a Q1 feature that cancels cable, bias-tee, and chip-level distortion on the FPGA in real time. It applies an inverse high-pass filter plus 4x IIR and FIR stages before a pulse leaves the sequencer.
Can Q1 calibrate qubits in real time?
Yes. A golden-section search runs directly in Q1ASM, in parallel across every qubit's sequencer, recalibrating resonance frequency, qubit frequency, gate amplitude, and T1. Running calibration inside the control system, rather than through a host PC over Ethernet.
Do I have to write Q1ASM, or can I work at a higher level?
Both paths exist. Qblox Scheduler is a Python package that compiles quantum circuits into Q1ASM files, uploads them to the right sequencers, and analyzes the results. Qblox Instruments is the low-level API for settings, programs, waveforms, and data. Teams can also write Q1ASM directly or target the open instruction set from their own compiler.
Discuss Q1 for your qubit requirements
A Qblox specialist can walk you through for your qubit platform, channel count, and calibration routines.
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